![cmos transistor cmos transistor](http://1.bp.blogspot.com/-KS7Eky8DL3M/TVP8VuNtfWI/AAAAAAAAAXw/JYjUKABGjc0/s1600/4.48.png)
The propagation delay high to low (t pHL) is the delay when output switches from high-to-low, after input switches from low-to-high. Many designs could also prefer 30% to 70% for rise time and 70% to 30% for fall time. Fall time (t f) is the time, during transition, when output switches from 90% to 10% of the maximum value. Rise time (t r) is the time, during transition, when output switches from 10% to 90% of the maximum value. In the above figure, there are 4 timing parameters.
![cmos transistor cmos transistor](https://holooly.com/wp-content/uploads/2022/07/%D9%A2%D9%A0%D9%A2%D9%A2%D9%A0%D9%A7%D9%A2%D9%A6_%D9%A2%D9%A1%D9%A2%D9%A7%D9%A2%D9%A0.jpg)
inverter is the difference in time (calculated at 50% of input-output transition), when output switches, after application of input. The propagation delay of a logic gate e.g. This would be more clear in the next section. The time required for change in ‘Vo’ after application of ‘Vi’, is called as propagation delay of the inverter. But, ‘Vo’ doesn’t changes instantaneously, but after a finite amount of delay after application of ‘Vi’. We understand that when ‘Vi’ switches from low to high (or high to low), ‘Vo’ switches from high to low (or low to high). Hence, during this mode of operation, C L discharges to Vss, through Rn, and ‘Vo’ switches from logic ‘1’ to logic ‘0’, as shown in figure below. This behavior could be modeled as an ‘open switch’ for PMOS and resistance ‘Rn’ for NMOS followed by a capacitor C L. Now, when ‘Vi’ switches from low to high, PMOS turns ‘OFF’, whereas NMOS turns ‘ON’. Hence, during the above mode of operation, C L charges to Vdd, through Rp, and ‘Vo’ switches from logic ‘0’ to logic ‘1’. Also, the wires connected to Vi and Vo of the inverter contribute to the load capacitance C L. These transistors contribute to lot of capacitance, which contribute to C L, load capacitance. In a large circuit, every CMOS is superseded and/or preceded by logic gates, which is again, nothing but a bunch of NMOS and PMOS transistors. During this operation of CMOS inverter, NMOS is modeled as an ‘open switch’, whereas PMOS is modeled as a resistance ‘Rp’ followed by a capacitor C L. When ‘Vi’ switches from high to low, PMOS turns ‘ON’ whereas NMOS turns ‘OFF’. Now, let us look at the transient response of an inverter.